A Unified Framework for Fault-Tolerant Power Electronics Modeling

Thesis Abstract

In the rapidly evolving field of power electronics, fault tolerance remains a critical bottleneck for ensuring reliability, safety, and continuous operation across renewable energy interfaces, electric vehicles, and industrial drives. This study addresses the persistent gap between fault-tolerant control strategies and comprehensive modeling that unifies device, circuit, and system-level dynamics under diverse fault scenarios. The aim is to develop a unified modeling framework that integrates physics-based device models, topology-aware circuit representations, and probabilistic fault behavior to enable provable resilience metrics for power electronics systems. The specific objectives are (1) to formulate a multi-scale, physics-informed model that couples semiconductor device degradation mechanisms with switching-level behavior; (2) to construct a topology-aware fault taxonomy and incorporate it into a unified state-space representation; (3) to develop a probabilistic reliability layer employing Markovian and Bayesian approaches to quantify fault propagation and recovery under operational stress; (4) to validate the framework against benchmark converters (DC-DC, inverters, and motor drives) experiencing intentional faults including short-circuits, open-circuits, parameter drifts, and thermal runaway; and (5) to derive resilience metrics and design guidelines for fault-tolerant operation, control reconfiguration, and diagnostic decision support. The methodology adopts a sequential explanatory mixed-methods design rooted in systems theory and reliability engineering. The research will employ a mixed population comprising 60 commercial and 20 wide-bandgap-oriented silicon carbide (SiC) and gallium nitride (GaN) power devices tested under accelerated aging conditions. Data collection will involve (i) high-fidelity circuit simulations using SPICE with parasitic models and physics-based device models, (ii) laboratory experiments on three representative converter topologies using a programmable load bank and thermal chamber to induce controlled faults, and (iii) field data from industrial drives to capture real-world fault patterns. Instrumentation includes high-speed data acquisition (?1 MHz sampling) for voltage, current, temperature, and switching signals; device failure logs; and diagnostic outputs from built-in self-test modules. Validity and reliability will be established through cross-validation of simulation results with hardware-in-the-loop (HIL) experiments and adherence to traceable calibration standards. Data analysis will combine quantitative and qualitative techniques (i) regression analysis and time-series forecasting to quantify fault impact on performance margins, (ii) stochastic modeling using Markov chains and Bayesian networks to capture fault progression and recovery probabilities, (iii) modal and sensitivity analysis to identify dominant fault pathways and parameter sensitivities, (iv) ANOVA and multivariate analysis to compare topology-induced resilience across device chemistries and operating regimes, and (v) thematic analysis of diagnostic logs to extract actionable fault signatures. The analytical framework will be implemented in a unified modeling environment that interlinks device physics, circuit dynamics, and reliability forecasting. Expected findings include (i) a cohesive multi-scale model that accurately predicts performance degradation and fault propagation under thermal, electrical, and aging stresses; (ii) a probabilistic resilience metric set enabling comparative assessment of fault-tolerant configurations and control reconfigurations; (iii) validated guidelines for selecting device technologies and topologies that optimize reliability without compromising efficiency; and (iv) a diagnostic decision-support framework capable of early fault detection, isolation, and mitigation strategies embedded within a model-based controller. The study contributes to knowledge by delivering the first integrated framework that harmonizes physics-based device models with topology-aware circuit representations and probabilistic reliability analysis for fault-tolerant power electronics. It provides a transferable modeling approach applicable to grid-tied converters, electric vehicle powertrains, and industrial drives, along with design guidelines and diagnostic strategies that bridge the gap between theoretical resilience and practical implementation. The central conclusion anticipates that the unified framework significantly enhances prediction accuracy of fault impact and enables proactive fault management, thereby extending mean time between failures and reducing downtime. Recommendations include adopting a standardized data collection protocol for fault signatures, integrating the framework into HIL testing for new converter designs, and extending the model to accommodate emerging wide-bandgap materials as standard practice in reliability-oriented design.