Edge-Aware Real-Time Image Compression on Embedded SoCs

Thesis Abstract

Edge-Aware Real-Time Image Compression on Embedded SoCs presents a rigorous investigation into delivering high-quality visual data with minimal latency on resource-constrained hardware. The study addresses the growing demand for bandwidth-efficient, low-latency image processing in mobile and edge environments, where conventional codecs struggle to balance computational load, energy consumption, and perceptual quality. The primary aim is to design, implement, and evaluate an edge-aware real-time image compression framework optimized for heterogeneous embedded Systems on Chips (SoCs) that integrates content-adaptive quantization, edge-preserving filtering, and hardware-friendly entropy coding. Specific objectives include (1) developing an edge-aware compression pipeline that leverages Canny-inspired edge maps and saliency cues to adapt quantization and transform parameters; (2) implementing the framework on a representative embedded platform, using the NXP i.MX 8M Plus SoC as a testbed; (3) evaluating rate-distortion performance, power efficiency, and latency under varying scene complexity and motion; (4) comparing the approach against standard codecs (e.g., HEVC-Intra, AVIF) in terms of objective quality metrics and perceptual user studies; and (5) providing a comprehensive design-space analysis and guidelines for deployment in real-time edge applications. The methodology adopts a design, implementation, and evaluation paradigm anchored in a mixed-methods approach. The population comprises embedded devices equipped with computer vision accelerators and heterogeneous CPU/GPU pipelines. A purposive sample of five real-world datasets is used a 1280×720 video corpus with diverse textures, a 720p surveillance sequence, a robotics navigation dataset, a medical-imaging surrogate sequence, and a synthetic high-motion scene, totaling approximately 120 minutes of footage. Data collection employs synthetic and real sensor streams aligned to standard video test sequences, with ground-truth references generated via lossless encoding. The core instrument comprises a modular compression engine implemented in C++ with CUDA/OpenCL kernels for edge detection, adaptive transform sizing, context-adaptive binary arithmetic coding, and a hardware-friendly entropy coder. Validity and reliability are ensured through cross-validation across datasets, ablation studies, and reproducible performance metrics. The data analysis employs a combination of objective metrics (PSNR, SSIM, VMAF, perceptual quality indices) and statistical techniques, including repeated-measures ANOVA to assess latency and quality trade-offs across configurations, regression analysis to model rate-distortion-power relationships, and non-parametric tests where applicable. An extensive computational performance profile is constructed to quantify throughput, energy per frame, and peak power under varied workloads. The analytical framework integrates established theories from information theory and perceptual psychology. Rate-distortion theory guides the optimization of quantization and transform block sizes under a perceptual loss model, while the edge-preserving priors inform edge-aware filtering and content-adaptive quantization boundaries. The study also mobilizes the Saliency-Driven Compression Hypothesis to justify the allocation of bits to salient regions and integrates a hardware-aware optimization theory to align software decisions with memory bandwidth and cache behavior. A conceptual model is proposed, linking scene complexity, edge density, and motion to adaptive bitrate decisions, encoder complexity, and latency, with feedback loops to accommodate dynamic scenes. Expected findings indicate that the edge-aware framework achieves comparable perceptual quality to standard codecs at 20–35% lower bitrate for scenes with pronounced edge structure, while maintaining sub-40 ms end-to-end latency for 720p real-time streaming on the chosen SoC. Power efficiency is anticipated to improve by 15–25% relative to baseline HEVC-Intra encoders under similar quality constraints, particularly in sequences with high edge density. The study is expected to demonstrate robust performance across diverse content types and to identify optimal parameter regimes for hardware-constrained deployments. Contributions to knowledge include (i) a novel edge-aware real-time compression paradigm tailored for embedded SoCs, (ii) a comprehensive evaluation framework and benchmark datasets for edge-aware video compression on constrained hardware, and (iii) practical design guidelines and a reference implementation that can be extended to other heterogeneous platforms. The study concludes that perceptual-aware, content-adaptive encoding on embedded architectures can substantially reduce bandwidth and energy consumption while satisfying real-time constraints, and it recommends further work on integrated on-chip learning for adaptive mode switching and broader cross-platform validation.