The design and implementation of an electronic sign pattern display

• Fig. 3.1: Block Diagram of a Dynamic Sign Display Fig. 3.2: Arrangement of the Pattern Display Fig. 4.1: Transformer Arrangement Fig. 4.2: Bridge Rectifier Fig. 4.3: Voltage and Current WaveformsFig. 4.4: Full Diagrams of Power Supply Fig. 5.1: Four Bit Series in Parallel out Register Logic Circuit ArrangementFig. 5.2: Clear and Shift SequenceFig. 5.3: Circuit Diagram  for SR Ftip-Flop Fig. 5.4: Timing Diagram for SR Ftip-Flop UnclockedFig. 4.4.B: Clocke CircuitFig. 6.1: Transistor Switch/Relay DriveFig. 6.2: Wave form of a Monostable, Fti-FlopFig. 7.1: Astable Multivibrator Fig. 7.2: Internal Block Diagram of CMOS555 TimerFig. 7.3: 555CMOS Connection as a Multivibrator Fig. 7.4: 555CMOS Connection as a TimerFig. 7.5: 555CMOS Connection as a Monostable Vibrator Fig. 8.1: Asynchroneous Decade Counter using Reset Fig. 8.2: Asynchroneous Decade Using FeedbackFig. 8.3: Timing Wave formFig. 8.4: Pin configuration of Latch CounterFig. 8.5: Circuit Diagrams of a Divided Counter Fig. 8.6: Complete Circuit Diagram of Electronics Sign PostFig. 8.7: Complete Picture of Electronic Sign Post  TABLE OF CONTENTSTitle Page Declaration Approval PageDedication AcknowledgementsList of Table List of Figure Table of Contents Abstract Description/Functions of Components Used with List of FiguresCHAPTER ONE Introduction

Chapter TWO

LITERATURE REVIEW

•  Literature reviewCHAPTER THREEMethodology

Chapter FOUR

DATA PRESENTATION AND ANALYSIS

• Power supplyRectification Filtration

Chapter FIVE

SUMMARY, CONCLUSION AND RECOMMENDATIONS

• Design of sequential Counter CHAPTER SIX Design of the transistor/Relay Drive CHAPTER SEVEN Design of system timing circuit Design of an interated timing circuit Astable multivbrator Asignchronous counter Synchronous counterCHAPTER EIGHT Construction and packaging Packaging Problem encountered and solutions References