Fig. 3.1: Block Diagram of a Dynamic Sign Display

Fig. 3.2: Arrangement of the Pattern Display

Fig. 4.1: Transformer Arrangement

Fig. 4.2: Bridge Rectifier

Fig. 4.3: Voltage and Current Waveforms

Fig. 4.4: Full Diagrams of Power Supply

Fig. 5.1: Four Bit Series in Parallel out Register Logic Circuit Arrangement

Fig. 5.2: Clear and Shift Sequence

Fig. 5.3: Circuit Diagram  for SR Ftip-Flop

Fig. 5.4: Timing Diagram for SR Ftip-Flop Unclocked

Fig. 4.4.B: Clocke Circuit

Fig. 6.1: Transistor Switch/Relay Drive

Fig. 6.2: Wave form of a Monostable, Fti-Flop

Fig. 7.1: Astable Multivibrator

Fig. 7.2: Internal Block Diagram of CMOS555 Timer

Fig. 7.3: 555CMOS Connection as a Multivibrator

Fig. 7.4: 555CMOS Connection as a Timer

Fig. 7.5: 555CMOS Connection as a Monostable Vibrator

Fig. 8.1: Asynchroneous Decade Counter using Reset

Fig. 8.2: Asynchroneous Decade Using Feedback

Fig. 8.3: Timing Wave form

Fig. 8.4: Pin configuration of Latch Counter

Fig. 8.5: Circuit Diagrams of a Divided Counter

Fig. 8.6: Complete Circuit Diagram of Electronics Sign Post

Fig. 8.7: Complete Picture of Electronic Sign Post  

TABLE OF CONTENTS

Title Page

Declaration

Approval Page

Dedication

Acknowledgements

List of Table

List of Figure

Table of Contents

Abstract

Description/Functions of Components Used with

List of Figures

Chapter ONE

Introduction

Chapter TWO

Literature review

Chapter THREE

Methodology

Chapter FOUR

Power supply

Rectification

Filtration

Chapter FIVE

Design of sequential Counter

CHAPTER SIX 

Design of the transistor/Relay Drive

CHAPTER SEVEN 

Design of system timing circuit

Design of an interated timing circuit

Astable multivbrator

Asignchronous counter

Synchronous counter

CHAPTER EIGHT

Construction and packaging

Packaging

Problem encountered and solutions

References